module link_test(/*GEN_PORT*/
);

input clk;

//GEN_INPUT
//GEN_OUTPUT
//GEN_WIRE

/*ctrl_unit u_ctrl LINK_MODULE
.SEL1_WD    (5)
.write(ctrl2mem_write),
.load_(.*)(LINK_load_#1#),
.mux2_sel_to_bus2(),
.zero_flag(1'b1),
*/

/*processing_unit u_proc LINK_MODULE
.SEL1_WD    (5)
.load_(.*)(LINK_load_#1#)
.mem_word(mem_word)
.bus1(proc2mem_data)
.addr(proc2mem_addr)
*/

/*mem_unit u_mem LINK_MODULE
.write_en(ctrl2mem_write)
.data_out(mem_word)
.data_in(proc2mem_data)
.addr_in(proc2mem_addr)
*/

ctrl_unit #(/*GEN_PARA*/) u_ctrl(/*GEN_LINK*/);

processing_unit u_proc(/*GEN_LINK*/);

mem_unit u_mem(/*GEN_LINK*/);

endmodule
//SUB MODULE LIST START
//"./"
//"./RISC_SPM/src","/home/xiaotu/my_work"
//SUB MODULE LIST END
